Spot defect modeling: Past and evolution

With today manufacturing technology, it is not possible to eliminate all defects and ensure every manufactured unit is perfect. Instead, each manufactured unit must be tested so that defective parts are not shipped to a customer. Different Test Strategies are commonly used since none is considered as optimal in terms of low defect level. Most companies use some but not all of the following three Test Strategies: the Static Voltage strategy, the Dynamic Voltage or Delay strategy, the Static or Dynamic Current (I_DDX) strategy. While using different approaches, these different test strategies have a common objective: reveal the presence in the chip of defects or deviations that may create a dysfunction. Knowing the complexity of today defects, it is admitted that the classical fault models used for test generation cannot guarantee a satisfactory detection of defects. This implies that new test generation technique specifically oriented to defects have to be defined. So, we must analyze and understand the electrical behavior of the defect and describe its behavior through an adequate ‘defect model’. Then, defect simulation techniques and defect-oriented ATPG techniques must be proposed to allow specific test generation for these defects. This presentation focuses on spot defects that manifest themselves as shorts or opens in the interconnect or in the MOS transistors: ‘Interconnect open’, ‘Interconnect short’, ‘Floating gate’, and ‘Gate-Oxide-Short’ are analyzed in detail using different model levels. For every defect, it is shown that the electrical behavior is in fact not predictable due to the presence of random parameters. In order to tackle the problem of unpredictability, unified concepts are proposed that allow new test generation techniques guaranteeing coverage of unpredictable defects.