13.5 mw, 5 ghz WLAN, CMOS频率合成器，使用真正的单相时钟分频器

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408) Pub Date : 2003-06-12 DOI:10.1109/VLSIC.2003.1221185

S. Pellerano, C. Samori, S. Levantino, A. Lacaita

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引用次数: 6

摘要

在0.25 /spl mu/m CMOS技术中演示了一个集成的5 GHz频率合成器，从2.5 V电源消耗仅5.4 mA。合成器内的分频器采用真单相时钟逻辑。输出频率从5.14到5.70 GHz，步进为20 MHz。参考杂散为-70 dBc，在整个调谐范围内，在1 MHz偏移时相位噪声低于-116 dBc/Hz。该合成器适用于HiperLAN II和IEEE 802.11a标准。

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13.5-mW, 5-GHz WLAN, CMOS frequency synthesizer using a true single phase clock divider

An integrated 5 GHz frequency synthesizer consuming only 5.4 mA from a 2.5 V supply is demonstrated in 0.25 /spl mu/m CMOS technology. The divider within the synthesizer employs the True Single Phase Clock logic. The output frequency spans from 5.14 to 5.70 GHz, with steps of 20 MHz. The reference spurs are -70 dBc and the phase noise is lower than -116 dBc/Hz at 1 MHz offset over the whole tuning range. The synthesizer is suitable for the HiperLAN II and the IEEE 802.11a standards.

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来源期刊

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)

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