一个56Gb/s的反串行器，带有PAM-4 CDR，用于Chiplet光i /O

2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) Pub Date : 2022-10-28 DOI:10.1109/ICTA56932.2022.9963101

Yunqiang Yang, Ming Zhong, Qianli Ma, Ziyi Lin, Leliang Li, Guike Li, Liyuan Liu, Jian Liu, N. Wu, Haikun Jia, Xinghui Liu, Nan Qi

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引用次数: 0

摘要

本文提出了一种基于PAM-4 CDR的56Gb/s反串行器，用于28nm CMOS芯片的光输入/输出。这个芯片有两个通道。每个通道由高性能模拟前端(AFE)和基于数字相位插值器和数字环路滤波器的半速率时钟和数据恢复(CDR)电路组成。为了向两个通道提供28ghz的时钟信号，集成了时钟分配电路。实验结果表明，该反串行器可以恢复56Gb/s的PAM-4输入信号，并具有信道损耗，输出摆幅为1.01 vppd, RMS抖动为760ps。

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A 56Gb/s De-serializer with PAM-4 CDR for Chiplet Optical-I/O

This paper presents a 56Gb/s de-serializer with PAM-4 CDR for chiplet optical-I/O in 28nm CMOS. There are two channels in this chip. Each channel consists of a high-performance analog front end (AFE) and a half-rate clock and data recovery (CDR) circuit based on a digital phase interpolator and digital loop filter. To provide 28-GHz clock signals to both channels, a clock distribution circuit is integrated. Experimental results show that the proposed de-serializer recovers a 56Gb/s PAM-4 input signal with channel loss, achieving an output swing of 1.01-Vppd and 760ps RMS jitter.

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2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)

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