Design of 50 MHz PLL using indigenous SCL 180 nm CMOS Technology

This paper presents a low power phase-locked loop implementation in indigenous SCL 180 nm CMOS technology. Fabricated PLL chip occupies an area of $0.005 mm^{2}$ including phase frequency detector, charge pump, current starved voltage controlled oscillator and divide by 4 block. An off-chip passive loop filter is used due to fab limitations. The frequency range of PLL varies from 10 to 105 MHz as shown in test results. The PLL chip consumes 0.28 mA ($\approx 500 \mu \mathrm{W})$ from a 1.8 V supply while producing 50 MHz output clock. The measured phase noise is -100 dBc/Hz at 100 kHz.