基于肖特基二极管的8.5pJ/bit超低功耗唤醒接收器

Mahmoud R. Elhebeary, Li-Yang Chen, S. Pamarti, C. Yang
{"title":"基于肖特基二极管的8.5pJ/bit超低功耗唤醒接收器","authors":"Mahmoud R. Elhebeary, Li-Yang Chen, S. Pamarti, C. Yang","doi":"10.1109/ESSCIRC.2019.8902825","DOIUrl":null,"url":null,"abstract":"In this paper, we present an always-on ultra-low power (ULP) wake-up receiver (WuRx) that constantly listens to the channel. We propose a two-phase WuRx architecture resulting in a 12% reduction in the average power consumption compared to conventional single-phase architectures. The first phase detects the existence of a signal and triggers the second phase responsible for signature detection. A CMOS integrable Schottky diode is proposed for power detection utilizing passive gain from impedance matching network. In the second phase, we propose a novel, low power data-locked startable oscillator to correlate the received data with predefined signature, which avoids the use of power-hungry crystal oscillator and features 1nW/kHz efficiency. The proposed system operates at 750MHz and achieves a low wake-up latency of 200µs, a -50dBm sensitivity at a data rate of 200 kbps, a 1.69 µW average power and achieves a FOM~8.5pJ/bit. The system is implemented in 65nm CMOS technology and occupies an area of 1mm×0.75mm.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"An 8.5pJ/bit Ultra-Low Power Wake-Up Receiver Using Schottky Diodes for IoT Applications\",\"authors\":\"Mahmoud R. Elhebeary, Li-Yang Chen, S. Pamarti, C. Yang\",\"doi\":\"10.1109/ESSCIRC.2019.8902825\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we present an always-on ultra-low power (ULP) wake-up receiver (WuRx) that constantly listens to the channel. We propose a two-phase WuRx architecture resulting in a 12% reduction in the average power consumption compared to conventional single-phase architectures. The first phase detects the existence of a signal and triggers the second phase responsible for signature detection. A CMOS integrable Schottky diode is proposed for power detection utilizing passive gain from impedance matching network. In the second phase, we propose a novel, low power data-locked startable oscillator to correlate the received data with predefined signature, which avoids the use of power-hungry crystal oscillator and features 1nW/kHz efficiency. The proposed system operates at 750MHz and achieves a low wake-up latency of 200µs, a -50dBm sensitivity at a data rate of 200 kbps, a 1.69 µW average power and achieves a FOM~8.5pJ/bit. The system is implemented in 65nm CMOS technology and occupies an area of 1mm×0.75mm.\",\"PeriodicalId\":402948,\"journal\":{\"name\":\"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)\",\"volume\":\"34 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.2019.8902825\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2019.8902825","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5

摘要

在本文中,我们提出了一种持续监听信道的超低功耗(ULP)唤醒接收器(WuRx)。我们提出了一种两相WuRx架构,与传统的单相架构相比,平均功耗降低了12%。第一阶段检测信号的存在并触发负责签名检测的第二阶段。提出了一种利用阻抗匹配网络无源增益进行功率检测的CMOS可积肖特基二极管。在第二阶段,我们提出了一种新颖的低功耗数据锁定可启动振荡器,将接收到的数据与预定义签名相关联,从而避免了耗电晶体振荡器的使用,并具有1nW/kHz的效率。该系统工作频率为750MHz,唤醒延迟低至200µs,数据速率为200kbps时灵敏度为-50dBm,平均功率为1.69µW, FOM为8.5pJ/bit。该系统采用65nm CMOS技术,占地面积为1mm×0.75mm。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An 8.5pJ/bit Ultra-Low Power Wake-Up Receiver Using Schottky Diodes for IoT Applications
In this paper, we present an always-on ultra-low power (ULP) wake-up receiver (WuRx) that constantly listens to the channel. We propose a two-phase WuRx architecture resulting in a 12% reduction in the average power consumption compared to conventional single-phase architectures. The first phase detects the existence of a signal and triggers the second phase responsible for signature detection. A CMOS integrable Schottky diode is proposed for power detection utilizing passive gain from impedance matching network. In the second phase, we propose a novel, low power data-locked startable oscillator to correlate the received data with predefined signature, which avoids the use of power-hungry crystal oscillator and features 1nW/kHz efficiency. The proposed system operates at 750MHz and achieves a low wake-up latency of 200µs, a -50dBm sensitivity at a data rate of 200 kbps, a 1.69 µW average power and achieves a FOM~8.5pJ/bit. The system is implemented in 65nm CMOS technology and occupies an area of 1mm×0.75mm.
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