Read disturb-free SRAM bit-cell for subthreshold memory applications

In this work, we present a novel bit-cell which improves data stability in subthreshold SRAM operation. It consists of eight transistors, two of which cut off a positive feedback of cross-coupled inverters during the read access. In addition, the bit-cell keeps the noise-vulnerable data ‘low’ node voltage close to the ground level during the dummy-read operation, and thus producing near-ideal voltage transfer characteristics essential for robust SRAM functionality. In the write access, the boosted wordline facilitates to change the contents of the memory bit. Implementation results in a 180 nm CMOS technology exhibit that the proposed cell remains unaffected by the read disturbance, while achieves 58.7 % higher dummy read stability and 3.68 × better write-ability at 0.4 V supply compared to the standard 6T SRAM cell.