I-Cache Tag Reduction for Low Power Chip Multiprocessor

Energy consumption is a major consideration in microprocessor optimization. This paper presents a tag-reduction based approach for energy saving in L1 I-Cache (instruction cache) of Chip Multiprocessors (CMP). To our best knowledge, this is the first work that extends the tag reduction technique to the CMP. We formulate our approach to an equivalent problem which is to find an assignment of the whole instruction pages in the physical memory to a set of cores such that the tag-reduction conflicts for each core can be mostly avoided or reduced. We then propose three algorithms using different heuristics for this assignment problem. The experimental results show that our proposed algorithms can save the total power up to 45.33% in average compared to the one that the tag-reduction is not used. They outperform significantly the tag-reduction based algorithm on single-core processor as well.