V. Subramanian, Van-Hoang Do, W. Keusgen, G. Boeck
{"title":"60 GHz SiGe HBT downconversion mixer","authors":"V. Subramanian, Van-Hoang Do, W. Keusgen, G. Boeck","doi":"10.1109/EMICC.2007.4412651","DOIUrl":null,"url":null,"abstract":"This work presents an active downconverter targeted for integration in 60 GHz high speed data communication RF front-ends. The designed downconverter has been realized in 0.25 mum SiGe BiCMOS technology with ft around 200 GHz. The downconverter consists of a single balanced mixer with an on-chip balun for differential to single ended conversion. High linearity and bandwidth are the main design goals rather than high gain. A clear-cut investigation of the applied bottom up design approach was presented with emphasis on modeling the critical on-chip signal path interconnects, matching and filtering components. The design and applied methodologies will be justified by comparing the measured and simulated performances. At 60 GHz an input 1-dB power compression of -5 dBm, 2.5 dB conversion gain and a gain variation around 2 dB from 50 to 70 GHz, are measured. Current consumption of the mixer core is 4.7 mA from a 3.3 V supply and the active chip area is 0.48 mm2.","PeriodicalId":436391,"journal":{"name":"2007 European Microwave Integrated Circuit Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-12-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 European Microwave Integrated Circuit Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EMICC.2007.4412651","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This work presents an active downconverter targeted for integration in 60 GHz high speed data communication RF front-ends. The designed downconverter has been realized in 0.25 mum SiGe BiCMOS technology with ft around 200 GHz. The downconverter consists of a single balanced mixer with an on-chip balun for differential to single ended conversion. High linearity and bandwidth are the main design goals rather than high gain. A clear-cut investigation of the applied bottom up design approach was presented with emphasis on modeling the critical on-chip signal path interconnects, matching and filtering components. The design and applied methodologies will be justified by comparing the measured and simulated performances. At 60 GHz an input 1-dB power compression of -5 dBm, 2.5 dB conversion gain and a gain variation around 2 dB from 50 to 70 GHz, are measured. Current consumption of the mixer core is 4.7 mA from a 3.3 V supply and the active chip area is 0.48 mm2.