{"title":"一种自适应反馈高压弹性浮动全量程电平移位器","authors":"Siddharth Katare, S. Alapati","doi":"10.1109/ICEEE49618.2020.9102481","DOIUrl":null,"url":null,"abstract":"With reduction in core voltage for digital logic, the design of low voltage (LV) to high voltage (HV) level shifter to support standard input-output interface poses several challenges. The floating and full-scale level shifter are used to convert such LV signals to HV domain without stressing the devices. In this paper we present an adaptive high voltage level shifter which improves the switching speed of circuit with increasing any static current. The proposed circuit is designed on a 28nm FDSOI (Fully Depleted Silicon on Insulators) process and supports upto 200MHz transaction speed at 100fF load. The proposed circuit exhibits less variation across process, voltage and temperature while consuming $3.6\\mu \\mathrm{W}/\\text{MHz}$ typical dynamic power.","PeriodicalId":131382,"journal":{"name":"2020 7th International Conference on Electrical and Electronics Engineering (ICEEE)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An Adaptive Feedback High Voltage Resilient Floating and Full-Scale Level-Shifter\",\"authors\":\"Siddharth Katare, S. Alapati\",\"doi\":\"10.1109/ICEEE49618.2020.9102481\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"With reduction in core voltage for digital logic, the design of low voltage (LV) to high voltage (HV) level shifter to support standard input-output interface poses several challenges. The floating and full-scale level shifter are used to convert such LV signals to HV domain without stressing the devices. In this paper we present an adaptive high voltage level shifter which improves the switching speed of circuit with increasing any static current. The proposed circuit is designed on a 28nm FDSOI (Fully Depleted Silicon on Insulators) process and supports upto 200MHz transaction speed at 100fF load. The proposed circuit exhibits less variation across process, voltage and temperature while consuming $3.6\\\\mu \\\\mathrm{W}/\\\\text{MHz}$ typical dynamic power.\",\"PeriodicalId\":131382,\"journal\":{\"name\":\"2020 7th International Conference on Electrical and Electronics Engineering (ICEEE)\",\"volume\":\"52 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-04-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 7th International Conference on Electrical and Electronics Engineering (ICEEE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICEEE49618.2020.9102481\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 7th International Conference on Electrical and Electronics Engineering (ICEEE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICEEE49618.2020.9102481","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An Adaptive Feedback High Voltage Resilient Floating and Full-Scale Level-Shifter
With reduction in core voltage for digital logic, the design of low voltage (LV) to high voltage (HV) level shifter to support standard input-output interface poses several challenges. The floating and full-scale level shifter are used to convert such LV signals to HV domain without stressing the devices. In this paper we present an adaptive high voltage level shifter which improves the switching speed of circuit with increasing any static current. The proposed circuit is designed on a 28nm FDSOI (Fully Depleted Silicon on Insulators) process and supports upto 200MHz transaction speed at 100fF load. The proposed circuit exhibits less variation across process, voltage and temperature while consuming $3.6\mu \mathrm{W}/\text{MHz}$ typical dynamic power.