在CMOS 40纳米技术中用于纳秒脉冲处理时间的电荷敏感放大器

R. Kleczek, P. Grybos, R. Szczygiel
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引用次数: 3

摘要

对专用于x射线成像应用的读出前端电子器件的要求水平仍在增加,例如:输入脉冲的高计数率能力、低噪声、低功耗和低硅区占用噪声。问题是:如何在最小化硅面积的同时将前端电子模拟参数保持在理想的水平,这仍然很重要,特别是在基于像素的架构成像应用中。我们报道了一种用于像素半导体探测器的CMOS 40纳米技术的读出前端电子模拟部分的设计。它只包括一个工作在跨阻模式的电荷敏感放大器,其反馈电路基于克鲁门纳彻结构。它的功耗在几十μW以下,噪声性能ENC在100 e- rms左右,脉冲峰值时间tp在几ns左右。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Charge sensitive amplifier for nanoseconds pulse processing time in CMOS 40 nm technology
The level of requirements for a readout front-end electronics dedicated for X-ray imaging applications, such as: high count rate ability of input pulses, low noise, low power dissipation and low silicon area occupation noise, is still increasing. The question: what one can do to minimize silicon area and keep front-end electronics analog parameters at a desirable level at the same time, is still important especially in pixel based architecture imaging applications. We report on the design of a readout front-end electronics analog part in CMOS 40 nm technology dedicated for pixel semiconductor detectors. It consists only a charge sensitive amplifier operating in transimpedance mode, which feedback circuit is based on a Krummenacher architecture. It has power dissipation below tens of μW, noise performance ENC around 100 e- rms and pulse peaking time tp around few ns.
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