{"title":"VHDL中间格式标准化活动:现状与趋势","authors":"Alain Fonkoua, J. Rouillard","doi":"10.1109/EURDAC.1992.246189","DOIUrl":null,"url":null,"abstract":"The VIFASG is a Design Automation Standards Subcommittee (DASS) subgroup which was setup to develop a proposal for a standard intermediate format representation of VHSIC hardware description language (VHDL) models. The status of the current proposal and the remaining issues to be addressed are summarized.<<ETX>>","PeriodicalId":218056,"journal":{"name":"Proceedings EURO-DAC '92: European Design Automation Conference","volume":"47 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"VHDL intermediate format standardization activity: status and trends\",\"authors\":\"Alain Fonkoua, J. Rouillard\",\"doi\":\"10.1109/EURDAC.1992.246189\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The VIFASG is a Design Automation Standards Subcommittee (DASS) subgroup which was setup to develop a proposal for a standard intermediate format representation of VHSIC hardware description language (VHDL) models. The status of the current proposal and the remaining issues to be addressed are summarized.<<ETX>>\",\"PeriodicalId\":218056,\"journal\":{\"name\":\"Proceedings EURO-DAC '92: European Design Automation Conference\",\"volume\":\"47 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings EURO-DAC '92: European Design Automation Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EURDAC.1992.246189\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings EURO-DAC '92: European Design Automation Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EURDAC.1992.246189","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
VHDL intermediate format standardization activity: status and trends
The VIFASG is a Design Automation Standards Subcommittee (DASS) subgroup which was setup to develop a proposal for a standard intermediate format representation of VHSIC hardware description language (VHDL) models. The status of the current proposal and the remaining issues to be addressed are summarized.<>