数字阵列接收信道性能测量系统

Jihong Yan, Yuqing Ma, Zishu He
{"title":"数字阵列接收信道性能测量系统","authors":"Jihong Yan, Yuqing Ma, Zishu He","doi":"10.1109/COMPCOMM.2016.7924977","DOIUrl":null,"url":null,"abstract":"Digital array radar (DAR) is an important tendency of phased array radar (PAR). Since the DAR is equipped with many transmitting and receiving channels, the effectiveness of digital beam-forming (DBF) is affected by the channel performance. Thus, it is important to test the channel performance and calibrate the possible channel mismatch of each digital T/R modules before assembling. In this paper, a CPCI interface based on the channel performance measurement is introduced. In the hardware design of the system, FPGA is employed as a core for data accusation and storage through optical interface. The CPCI chip is used as the interface between the data acquisition board and PC. Under the control of computer application programs, the collected data are transferred back to the computer, in which the waveform analysis in both time and frequency domain and the calculation of the channel performance metrics are performed. The test results show the effectiveness and feasibility of the proposed design method.","PeriodicalId":210833,"journal":{"name":"2016 2nd IEEE International Conference on Computer and Communications (ICCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Digital array receiving channel performance measurement system\",\"authors\":\"Jihong Yan, Yuqing Ma, Zishu He\",\"doi\":\"10.1109/COMPCOMM.2016.7924977\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Digital array radar (DAR) is an important tendency of phased array radar (PAR). Since the DAR is equipped with many transmitting and receiving channels, the effectiveness of digital beam-forming (DBF) is affected by the channel performance. Thus, it is important to test the channel performance and calibrate the possible channel mismatch of each digital T/R modules before assembling. In this paper, a CPCI interface based on the channel performance measurement is introduced. In the hardware design of the system, FPGA is employed as a core for data accusation and storage through optical interface. The CPCI chip is used as the interface between the data acquisition board and PC. Under the control of computer application programs, the collected data are transferred back to the computer, in which the waveform analysis in both time and frequency domain and the calculation of the channel performance metrics are performed. The test results show the effectiveness and feasibility of the proposed design method.\",\"PeriodicalId\":210833,\"journal\":{\"name\":\"2016 2nd IEEE International Conference on Computer and Communications (ICCC)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 2nd IEEE International Conference on Computer and Communications (ICCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/COMPCOMM.2016.7924977\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 2nd IEEE International Conference on Computer and Communications (ICCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/COMPCOMM.2016.7924977","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

数字阵列雷达(DAR)是相控阵雷达(PAR)的一个重要发展方向。由于雷达具有多个发射和接收信道,信道性能直接影响数字波束形成的效果。因此,在组装之前测试通道性能并校准每个数字T/R模块可能的通道不匹配是很重要的。本文介绍了一种基于信道性能测量的CPCI接口。在系统的硬件设计中,采用FPGA作为核心,通过光接口进行数据采集和存储。CPCI芯片作为数据采集板与PC机之间的接口。在计算机应用程序的控制下,将采集到的数据传回计算机,进行时域和频域的波形分析和信道性能指标的计算。试验结果表明了所提设计方法的有效性和可行性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Digital array receiving channel performance measurement system
Digital array radar (DAR) is an important tendency of phased array radar (PAR). Since the DAR is equipped with many transmitting and receiving channels, the effectiveness of digital beam-forming (DBF) is affected by the channel performance. Thus, it is important to test the channel performance and calibrate the possible channel mismatch of each digital T/R modules before assembling. In this paper, a CPCI interface based on the channel performance measurement is introduced. In the hardware design of the system, FPGA is employed as a core for data accusation and storage through optical interface. The CPCI chip is used as the interface between the data acquisition board and PC. Under the control of computer application programs, the collected data are transferred back to the computer, in which the waveform analysis in both time and frequency domain and the calculation of the channel performance metrics are performed. The test results show the effectiveness and feasibility of the proposed design method.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信