具有低偏移动态比较器的闪存ADC

2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2017-10-01 DOI:10.1109/EDSSC.2017.8126480

Jia Liu, Fule Li, Weitao Li, Hanjun Jiang, Zhihua Wang

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引用次数: 3

摘要

本文提出了一种采用偏移抵消技术的具有低偏移动态比较器的Flash ADC。通过在输入电容上动态存储比较器偏移量，可以有效地抑制偏移量。两个5位160MS/s的Flash adc (Flash- a使用所提出的偏移抵消技术和Flash- b没有抵消)在65nm CMOS中制造以进行比较。测量结果表明，DNL从1.32LSB降低到0.62LSB, INL从1.20LSB降低到0.55LSB。SNDR从26.25dB提高到29.63dB, SFDR从35.02dB提高到43.61dB。功率从3.44 mW增加到3.79 mW。

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A flash ADC with low offset dynamic comparators

This paper presents a Flash ADC with low offset dynamic comparators using an offset cancellation technique. By dynamically storing the comparator offset on the input capacitors, the offset is suppressed mostly. Two 5-bit 160MS/s Flash ADCs (Flash-A using the proposed offset cancellation technique and Flash-B without cancellation) are fabricated in 65nm CMOS for comparison. The measure results show that, the DNL is reduced from 1.32LSB to 0.62LSB and the INL is reduced from 1.20LSB to 0.55LSB. The SNDR improves from 26.25dB to 29.63dB and the SFDR improves from 35.02dB to 43.61dB. And the power increases from 3.44 mW to 3.79 mW.

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来源期刊

2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)

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