Tong Lin, Kwen-Siong Chong, J. Chang, B. Gwee, Wei Shu
{"title":"一种实现超低功耗数字自适应VDD缩放系统的鲁棒异步方法","authors":"Tong Lin, Kwen-Siong Chong, J. Chang, B. Gwee, Wei Shu","doi":"10.1109/SUBVT.2012.6404298","DOIUrl":null,"url":null,"abstract":"Self-Adaptive VDD Scaling (SAVS) technique achieves power/energy reduction by dynamically scaling VDD for the prevailing conditions. However, when applied in sub-threshold (sub-Vt) region, robustness issues need to be addressed due to the severe delay uncertainty associated with sub-Vt Process, Voltage, and Temperature (PVT) variations. To ensure robustness for sub-Vt SAVS, we adopt the asynchronous-logic (async) Quasi-Delay-Insensitive (QDI) approach. To address the usual power/energy overheads associated with conventional async QDI systems, we further propose a hardware-simplified version of QDI (`pseudo-QDI') with an easy-to-met implicit timing. Prototype ICs embodying async filter banks realized in both the conventional QDI and pseudo-QDI have demonstrated the extreme robustness of the proposed approach against sub-Vt PVT variations. Measurement results further suggest pseudo-QDI's energy (~40% lower) and area (~1.34× smaller) advantages as compared to its conventional QDI counterpart.","PeriodicalId":383826,"journal":{"name":"2012 IEEE Subthreshold Microelectronics Conference (SubVT)","volume":"127 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A robust asynchronous approach for realizing ultra-low power digital Self-Adaptive VDD Scaling system\",\"authors\":\"Tong Lin, Kwen-Siong Chong, J. Chang, B. Gwee, Wei Shu\",\"doi\":\"10.1109/SUBVT.2012.6404298\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Self-Adaptive VDD Scaling (SAVS) technique achieves power/energy reduction by dynamically scaling VDD for the prevailing conditions. However, when applied in sub-threshold (sub-Vt) region, robustness issues need to be addressed due to the severe delay uncertainty associated with sub-Vt Process, Voltage, and Temperature (PVT) variations. To ensure robustness for sub-Vt SAVS, we adopt the asynchronous-logic (async) Quasi-Delay-Insensitive (QDI) approach. To address the usual power/energy overheads associated with conventional async QDI systems, we further propose a hardware-simplified version of QDI (`pseudo-QDI') with an easy-to-met implicit timing. Prototype ICs embodying async filter banks realized in both the conventional QDI and pseudo-QDI have demonstrated the extreme robustness of the proposed approach against sub-Vt PVT variations. Measurement results further suggest pseudo-QDI's energy (~40% lower) and area (~1.34× smaller) advantages as compared to its conventional QDI counterpart.\",\"PeriodicalId\":383826,\"journal\":{\"name\":\"2012 IEEE Subthreshold Microelectronics Conference (SubVT)\",\"volume\":\"127 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 IEEE Subthreshold Microelectronics Conference (SubVT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SUBVT.2012.6404298\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE Subthreshold Microelectronics Conference (SubVT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SUBVT.2012.6404298","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A robust asynchronous approach for realizing ultra-low power digital Self-Adaptive VDD Scaling system
Self-Adaptive VDD Scaling (SAVS) technique achieves power/energy reduction by dynamically scaling VDD for the prevailing conditions. However, when applied in sub-threshold (sub-Vt) region, robustness issues need to be addressed due to the severe delay uncertainty associated with sub-Vt Process, Voltage, and Temperature (PVT) variations. To ensure robustness for sub-Vt SAVS, we adopt the asynchronous-logic (async) Quasi-Delay-Insensitive (QDI) approach. To address the usual power/energy overheads associated with conventional async QDI systems, we further propose a hardware-simplified version of QDI (`pseudo-QDI') with an easy-to-met implicit timing. Prototype ICs embodying async filter banks realized in both the conventional QDI and pseudo-QDI have demonstrated the extreme robustness of the proposed approach against sub-Vt PVT variations. Measurement results further suggest pseudo-QDI's energy (~40% lower) and area (~1.34× smaller) advantages as compared to its conventional QDI counterpart.