{"title":"一种高直流增益折叠级联CMOS运算放大器","authors":"Wen Whe Sue, Zhi-Ming Lin, C. H. Huang","doi":"10.1109/SECON.1998.673321","DOIUrl":null,"url":null,"abstract":"The architecture of folded-cascode op-amp is commonly used in many analog applications. The cascode arrangement has high open-loop voltage gain in the low frequency range that make it easy to be designed as a high-speed operational amplifier. In this paper, we present the design of a fully differential folded-cascode operational amplifier that improves the limitation on the swing of the output signal of a common cascode architecture. The DC open-loop gain of the circuit is 4.7 K.","PeriodicalId":281991,"journal":{"name":"Proceedings IEEE Southeastcon '98 'Engineering for a New Era'","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"A high DC-gain folded-cascode CMOS operational amplifier\",\"authors\":\"Wen Whe Sue, Zhi-Ming Lin, C. H. Huang\",\"doi\":\"10.1109/SECON.1998.673321\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The architecture of folded-cascode op-amp is commonly used in many analog applications. The cascode arrangement has high open-loop voltage gain in the low frequency range that make it easy to be designed as a high-speed operational amplifier. In this paper, we present the design of a fully differential folded-cascode operational amplifier that improves the limitation on the swing of the output signal of a common cascode architecture. The DC open-loop gain of the circuit is 4.7 K.\",\"PeriodicalId\":281991,\"journal\":{\"name\":\"Proceedings IEEE Southeastcon '98 'Engineering for a New Era'\",\"volume\":\"11 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1998-04-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings IEEE Southeastcon '98 'Engineering for a New Era'\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SECON.1998.673321\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings IEEE Southeastcon '98 'Engineering for a New Era'","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SECON.1998.673321","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A high DC-gain folded-cascode CMOS operational amplifier
The architecture of folded-cascode op-amp is commonly used in many analog applications. The cascode arrangement has high open-loop voltage gain in the low frequency range that make it easy to be designed as a high-speed operational amplifier. In this paper, we present the design of a fully differential folded-cascode operational amplifier that improves the limitation on the swing of the output signal of a common cascode architecture. The DC open-loop gain of the circuit is 4.7 K.
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