W. Khaddour, F. Dadouche, W. Uhring, V. Frick, M. Madec
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引用次数: 1
摘要
已有数百篇研究论文从理论上讨论了在现场可编程门阵列(FPGA)目标上实现基于抽头延迟线的时间数字转换器(TDL tdc)。然而,这些工作大多没有涵盖由于路由延迟而遇到的时间问题。这项工作的目的是强调在FPGA目标中实现tdc时应考虑的主要时序问题,并提出克服这些问题的实用方法。作为一个研究案例,在本工作中提出了Cyclone V FPGA目标上TDC的完整设计方法。
Design Methodology and Timing Considerations for implementing a TDC on a Cyclone V FPGA Target
There are hundreds of research publications that theoretically discuss the implementation of Tapped Delay Line based Time to Digital Converters (TDL TDCs) on Field-Programmable Gate Array (FPGA) targets. However, most of these works do not cover the timing issues that will be encountered mostly due to the routing delays. The purpose of this work is to highlight the main timing issues that should be considered when implementing TDCs in FPGA targets and propose practical approaches to overcome these issues. As a study case, a full design methodology of a TDC on a Cyclone V FPGA target is presented in this work.