一种小型化低功耗卷积解码器架构

A. Demosthenous, J. Taylor
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引用次数: 2

摘要

卷积解码器在遇到噪声非常大的信道的应用中一直很重要。随着各种类型的移动无线电系统和数字磁记录系统等新应用领域的出现,该技术变得更加重要。最常用的解码技术是Viterbi算法(VA)。这为实现卷积解码器提供了一种最佳方法,但需要大量的数字存储器,通常高达芯片总面积的50%。本文提出了一种改进的反馈译码算法(MFDA)。这不需要数字路径存储器,因此可以完全使用模拟元件实现。虽然严格来说不是最优的,但对于K=5的编码,与VA相比,编码增益的损失仅为0.4 dB左右。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An architecture for miniaturised low power convolutional decoders
Convolutional decoders have long been important in applications where very noisy channels are encountered. The technique has become more significant with the advent of new application areas such as mobile radio systems of various types and digital magnetic recording systems. The most commonly employed decoding technique is the Viterbi algorithm (VA). This provides an optimum method for realising a convolutional decoder, but requires a large amount of digital memory, typically up to 50% of the total chip area. In this paper we describe an alternative method which we call the modified feedback decoding algorithm (MFDA). This requires no digital path memory and so can be realised entirely using analogue components. Although strictly sub-optimal, the loss of coding gain compared to the VA is only about 0.4 dB for a K=5 code.
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