Performance Enhancement of Non-uniformly Doped Junctionless Transistors by Gate and Dielectric engineering

In this paper, the use of laterally graded doping and hetero gate high dielectric with high-k spacers which were positioned on both sides of the gate have been proposed to improve the performance of Junctionless Transistors (JLT). Further recessed gate structure is also used to compare its performance with conventional JLTs. 2-D TCAD simulations have been used to observe that the Drain-Induced Barrier Lowering (DIBL) and Sub Threshold Swing (SS) were reduced by 26% and 61% respectively. Further the current ratio improved by 108 times in the final structure. Our analysis focuses on the ability of the proposed design for a reduced leakage current leading to higher current ratio and also lower short channel effects (SCEs) like SS and DIBL.