{"title":"安排半导体设备测试操作","authors":"T. Carmon-Freed","doi":"10.1109/IEMT.1996.559792","DOIUrl":null,"url":null,"abstract":"The problem of planning and scheduling the production of test facilities to maximize throughput and minimize cost has, therefore, been gaining importance for semiconductor manufacturers. In this paper, a classification scheme for semiconductor device testing environments is presented and various testing environments are described in detail. The mathematical models describing these test environments, and software packages intended to provide scheduling solutions for semiconductor device testing are mentioned.","PeriodicalId":177653,"journal":{"name":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","volume":"28 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Scheduling semiconductor device test operations\",\"authors\":\"T. Carmon-Freed\",\"doi\":\"10.1109/IEMT.1996.559792\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The problem of planning and scheduling the production of test facilities to maximize throughput and minimize cost has, therefore, been gaining importance for semiconductor manufacturers. In this paper, a classification scheme for semiconductor device testing environments is presented and various testing environments are described in detail. The mathematical models describing these test environments, and software packages intended to provide scheduling solutions for semiconductor device testing are mentioned.\",\"PeriodicalId\":177653,\"journal\":{\"name\":\"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium\",\"volume\":\"28 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-10-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEMT.1996.559792\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEMT.1996.559792","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The problem of planning and scheduling the production of test facilities to maximize throughput and minimize cost has, therefore, been gaining importance for semiconductor manufacturers. In this paper, a classification scheme for semiconductor device testing environments is presented and various testing environments are described in detail. The mathematical models describing these test environments, and software packages intended to provide scheduling solutions for semiconductor device testing are mentioned.