Vertical transistor deep trench DRAM failure analysis and failure mechanisms

Recent development of a vertical transistor deep trench capacitor DRAM cell revealed several new failure mechanisms and proved to be a challenge to traditional failure analysis techniques. The development was done on two test vehicles, an existing planar transistor 256 Mb design with an 8F/sup 2/ 175 nm ground rule cell was modified to use the vertical transistor and a 512 Mb 110 nm design was implemented with the vertical transistor. This paper gives examples of failure mechanisms found during the early phases of the development cycle and discusses the application of failure analysis techniques to the unique structures on the vertical transistor DRAM technology.