{"title":"减少开关数量的多电平逆变器拓扑结构","authors":"M. Kashif, Amir Khurrum Rashid","doi":"10.1109/INTELSE.2016.7475132","DOIUrl":null,"url":null,"abstract":"A novel multilevel inverter topology with reduced number of power switches is proposed. This new topology is based on a combination of conventional diode clamped and H-bridge topologies. The proposed idea has been validated through simulation results.","PeriodicalId":127671,"journal":{"name":"2016 International Conference on Intelligent Systems Engineering (ICISE)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"A multilevel inverter topology with reduced number of switches\",\"authors\":\"M. Kashif, Amir Khurrum Rashid\",\"doi\":\"10.1109/INTELSE.2016.7475132\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A novel multilevel inverter topology with reduced number of power switches is proposed. This new topology is based on a combination of conventional diode clamped and H-bridge topologies. The proposed idea has been validated through simulation results.\",\"PeriodicalId\":127671,\"journal\":{\"name\":\"2016 International Conference on Intelligent Systems Engineering (ICISE)\",\"volume\":\"10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 International Conference on Intelligent Systems Engineering (ICISE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/INTELSE.2016.7475132\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 International Conference on Intelligent Systems Engineering (ICISE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/INTELSE.2016.7475132","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A multilevel inverter topology with reduced number of switches
A novel multilevel inverter topology with reduced number of power switches is proposed. This new topology is based on a combination of conventional diode clamped and H-bridge topologies. The proposed idea has been validated through simulation results.