A Low Power 12-Bit Pipeline ADC with 40 MS/s using a Modified OP-AMP

Design of a 12-bit Pipeline Analog to Digital Converter (ADC) with a 40 MS/s sampling rate using a proposed modified Operational Amplifier (OP-AMP) is presented in this paper. The ADC architecture, consists of eleven pipeline stages of ten 1.5-bit pipelined ADC stages and one flash ADC with 2-bits resolution. This design is implemented by the 90-nm CMOS process. The power consumption of the ADC is reduced by various techniques, including sample and hold (SH) less architecture, OP-AMP sharing technique, and capacitor size scaling in pipeline stages of the ADC. FFT analysis which results in the Signal to Noise and Distortion Ratio (SNDR) of 71.22 dB which means the Effective Number Of Bits (ENOB) equal to 11.53 when $\mathrm{f}_{\mathrm{i}\mathrm{n}}$ is 4 MHz. The proposed 12-bit pipeline has 47.3 mW power consumption with a 1.2 V supply voltage.