F. Borghetti, A. Esposito, U. Gatti, P. Malcovati, F. Maloberti
{"title":"用于320兆赫2路σ - δ调制器的BiCMOS开关缓冲谐振器","authors":"F. Borghetti, A. Esposito, U. Gatti, P. Malcovati, F. Maloberti","doi":"10.1109/ISCAS.2002.1010219","DOIUrl":null,"url":null,"abstract":"In this paper we present a resonator circuit suitable for the implementation of high speed switched-capacitor n-path bandpass /spl Sigma//spl Delta/ modulators. The resonator, implemented using a 0.8 /spl mu/m SiGe BiCMOS process (f/sub T/=35 GHz), exploits switched buffers realized using bipolar transistors to emulate the CMOS switches behavior at much higher speed. The circuit has a resonance frequency of 77.5 MHz and operates at a clock frequency of 160 MHz, consuming 120 mA from a 5 V power supply. Moreover, simulations have confirmed that with the proposed technique clock frequencies up to 200 MHz can be used without significant degradation of the performance.","PeriodicalId":203750,"journal":{"name":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"BiCMOS switched buffers resonator for a 320 MHz 2-path sigma-delta modulator\",\"authors\":\"F. Borghetti, A. Esposito, U. Gatti, P. Malcovati, F. Maloberti\",\"doi\":\"10.1109/ISCAS.2002.1010219\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper we present a resonator circuit suitable for the implementation of high speed switched-capacitor n-path bandpass /spl Sigma//spl Delta/ modulators. The resonator, implemented using a 0.8 /spl mu/m SiGe BiCMOS process (f/sub T/=35 GHz), exploits switched buffers realized using bipolar transistors to emulate the CMOS switches behavior at much higher speed. The circuit has a resonance frequency of 77.5 MHz and operates at a clock frequency of 160 MHz, consuming 120 mA from a 5 V power supply. Moreover, simulations have confirmed that with the proposed technique clock frequencies up to 200 MHz can be used without significant degradation of the performance.\",\"PeriodicalId\":203750,\"journal\":{\"name\":\"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)\",\"volume\":\"38 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISCAS.2002.1010219\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCAS.2002.1010219","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
BiCMOS switched buffers resonator for a 320 MHz 2-path sigma-delta modulator
In this paper we present a resonator circuit suitable for the implementation of high speed switched-capacitor n-path bandpass /spl Sigma//spl Delta/ modulators. The resonator, implemented using a 0.8 /spl mu/m SiGe BiCMOS process (f/sub T/=35 GHz), exploits switched buffers realized using bipolar transistors to emulate the CMOS switches behavior at much higher speed. The circuit has a resonance frequency of 77.5 MHz and operates at a clock frequency of 160 MHz, consuming 120 mA from a 5 V power supply. Moreover, simulations have confirmed that with the proposed technique clock frequencies up to 200 MHz can be used without significant degradation of the performance.