J. Zeng, V. Joyner, J. Liao, Shengling Deng, Z. Huang
{"title":"用于自由空间光学MIMO的5Gb/s 7通道电流模式成像接收器前端","authors":"J. Zeng, V. Joyner, J. Liao, Shengling Deng, Z. Huang","doi":"10.1109/MWSCAS.2009.5236130","DOIUrl":null,"url":null,"abstract":"A 7-channel diversity receiver front-end based on current-summing for broadband free-space optical (FSO) MIMO communication is presented in this paper. This diversity receiver is designed for flip-chip bonding to a custom InGaAs metal-semiconductor-metal (MSM) photodetector array. Each channel employs a low input-impedance current mirror (CM) as the input stage, which allows the implementation of direct current-summing for equal-gain combining (EGC). The summed-up current signal drives a second stage transimpedance amplifier (TIA) to generate the output voltage. Implemented in an 180 nm CMOS technology, a total gain of 58.5 dBΩ, and −3dB bandwidth of 3.7 GHz for 0.25 pF photodiode capacitance is achieved. The power consumption for a single front-end amplifier circuit is 4.2 mW, and for the second stage TIA is 10.3mW with a single 1.8V supply.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"60 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"19","resultStr":"{\"title\":\"A 5Gb/s 7-channel current-mode imaging receiver front-end for free-space optical MIMO\",\"authors\":\"J. Zeng, V. Joyner, J. Liao, Shengling Deng, Z. Huang\",\"doi\":\"10.1109/MWSCAS.2009.5236130\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 7-channel diversity receiver front-end based on current-summing for broadband free-space optical (FSO) MIMO communication is presented in this paper. This diversity receiver is designed for flip-chip bonding to a custom InGaAs metal-semiconductor-metal (MSM) photodetector array. Each channel employs a low input-impedance current mirror (CM) as the input stage, which allows the implementation of direct current-summing for equal-gain combining (EGC). The summed-up current signal drives a second stage transimpedance amplifier (TIA) to generate the output voltage. Implemented in an 180 nm CMOS technology, a total gain of 58.5 dBΩ, and −3dB bandwidth of 3.7 GHz for 0.25 pF photodiode capacitance is achieved. The power consumption for a single front-end amplifier circuit is 4.2 mW, and for the second stage TIA is 10.3mW with a single 1.8V supply.\",\"PeriodicalId\":254577,\"journal\":{\"name\":\"2009 52nd IEEE International Midwest Symposium on Circuits and Systems\",\"volume\":\"60 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-09-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"19\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 52nd IEEE International Midwest Symposium on Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MWSCAS.2009.5236130\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2009.5236130","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 5Gb/s 7-channel current-mode imaging receiver front-end for free-space optical MIMO
A 7-channel diversity receiver front-end based on current-summing for broadband free-space optical (FSO) MIMO communication is presented in this paper. This diversity receiver is designed for flip-chip bonding to a custom InGaAs metal-semiconductor-metal (MSM) photodetector array. Each channel employs a low input-impedance current mirror (CM) as the input stage, which allows the implementation of direct current-summing for equal-gain combining (EGC). The summed-up current signal drives a second stage transimpedance amplifier (TIA) to generate the output voltage. Implemented in an 180 nm CMOS technology, a total gain of 58.5 dBΩ, and −3dB bandwidth of 3.7 GHz for 0.25 pF photodiode capacitance is achieved. The power consumption for a single front-end amplifier circuit is 4.2 mW, and for the second stage TIA is 10.3mW with a single 1.8V supply.