Chip-package co-design for high-speed transmitter in serial links application

As technology scales down, the performance of most digital systems is limited by their package, not by their logic because of package parasitics. In this paper, a chip-package co-design approach was used for high-speed transmitter design towards serial links application. Impedance-controlled signal channel and power efficient multi-level current-mode differential signaling were analyzed and used in order to improve the overall system performance and robustness. Simulation results show that noise margin is increased while time margin is decreased for impedance-controlled signal channel in the operation frequencies. In addition, it is found that the bipolar driver can reduce power consumption by a factor of 15% compared with current mode logic driver.