基于FPGA的正交直接数字频率合成器

2006 International Conference on Computer Engineering and Systems Pub Date : 2006-11-01 DOI:10.1109/ICCES.2006.320418

M. Saber, M. Elmasry, M. Abo-Elsoud

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引用次数: 2

摘要

提出了一种低功耗正交直接数字频率合成器(DDFS)。该系统基于经典的DDFS结构。为了避免高功耗，不使用ROM，而是采用分段线性逼近。系统采用FPGA实现，电源电压为3.3 V。功耗为3.96 mW。低合成频率下无杂散动态范围优于59 dBc，频率分辨率为1.5 kHz

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Quadrature Direct Digital Frequency Synthesizer Using FPGA

A low-power quadrature direct digital frequency synthesizer (DDFS) is presented. Such system is based on a classical DDFS structure. In order to avoid the high power consumption, no ROM is used but piecewise linear approximation is employed. The system is implemented using FPGA with 3.3 V supply voltage. The power consumption is 3.96 mW. The spurious-free dynamic range is better than 59 dBc at low synthesized frequencies and the frequency resolution is 1.5 kHz

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2006 International Conference on Computer Engineering and Systems

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