Rojalin Rout, T. Roy, T. R. Choudhury, B. Nayak, B. Mishra
{"title":"一种基于精简电力电子开关和直流电源的新型多电平逆变器结构分析与实现","authors":"Rojalin Rout, T. Roy, T. R. Choudhury, B. Nayak, B. Mishra","doi":"10.1109/ICRIEECE44171.2018.9009206","DOIUrl":null,"url":null,"abstract":"A novel structure of multilevel inverter is presented in this paper. The presented topology is a cascaded structure of novel sub-module basic unit which can produce 19 level output voltage. The sub-module consists of 3 asymmetric dc sources (V, 3V, 0.5V) and 12 switches. It is capable of generating both integral and fractional output levels. The basic unit is connected symmetrically in a cascade manner. Proposed topology is compared with other MLI topologies that have been recently developed in terms of a number of switches, gate driver circuits, and dc links. It is observed that this topology uses less number of components at a given level among in comparison to other topologies. Simulation of the proposed basic unit is done in MATLAB/SIMULINK. The circuit is verified for different load conditions such as R-L, L and sudden load change conditions. Total Harmonic Distortion of both output current and output voltage is also determined. This topology is found to generate output levels with very low Total Harmonic Distortion.","PeriodicalId":393891,"journal":{"name":"2018 International Conference on Recent Innovations in Electrical, Electronics & Communication Engineering (ICRIEECE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Analysis and Implementation of a Novel Multilevel Inverter Structure Using Reduced Power Electronic Switches and DC Sources\",\"authors\":\"Rojalin Rout, T. Roy, T. R. Choudhury, B. Nayak, B. Mishra\",\"doi\":\"10.1109/ICRIEECE44171.2018.9009206\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A novel structure of multilevel inverter is presented in this paper. The presented topology is a cascaded structure of novel sub-module basic unit which can produce 19 level output voltage. The sub-module consists of 3 asymmetric dc sources (V, 3V, 0.5V) and 12 switches. It is capable of generating both integral and fractional output levels. The basic unit is connected symmetrically in a cascade manner. Proposed topology is compared with other MLI topologies that have been recently developed in terms of a number of switches, gate driver circuits, and dc links. It is observed that this topology uses less number of components at a given level among in comparison to other topologies. Simulation of the proposed basic unit is done in MATLAB/SIMULINK. The circuit is verified for different load conditions such as R-L, L and sudden load change conditions. Total Harmonic Distortion of both output current and output voltage is also determined. This topology is found to generate output levels with very low Total Harmonic Distortion.\",\"PeriodicalId\":393891,\"journal\":{\"name\":\"2018 International Conference on Recent Innovations in Electrical, Electronics & Communication Engineering (ICRIEECE)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-07-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 International Conference on Recent Innovations in Electrical, Electronics & Communication Engineering (ICRIEECE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICRIEECE44171.2018.9009206\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 International Conference on Recent Innovations in Electrical, Electronics & Communication Engineering (ICRIEECE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICRIEECE44171.2018.9009206","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Analysis and Implementation of a Novel Multilevel Inverter Structure Using Reduced Power Electronic Switches and DC Sources
A novel structure of multilevel inverter is presented in this paper. The presented topology is a cascaded structure of novel sub-module basic unit which can produce 19 level output voltage. The sub-module consists of 3 asymmetric dc sources (V, 3V, 0.5V) and 12 switches. It is capable of generating both integral and fractional output levels. The basic unit is connected symmetrically in a cascade manner. Proposed topology is compared with other MLI topologies that have been recently developed in terms of a number of switches, gate driver circuits, and dc links. It is observed that this topology uses less number of components at a given level among in comparison to other topologies. Simulation of the proposed basic unit is done in MATLAB/SIMULINK. The circuit is verified for different load conditions such as R-L, L and sudden load change conditions. Total Harmonic Distortion of both output current and output voltage is also determined. This topology is found to generate output levels with very low Total Harmonic Distortion.