A constraints programming approach for fabric cell synthesis

This paper presents a novel method to generate optimized architecture of hardware processes implemented on "system on a programmable chip" (SoPC). The hardware processes are the applications tailored "cells" in the processor-coupled polymorphous fabric (Ch. Wolinski et al., 2003, Ch. Wolinski et al., 2002) implemented on the reconfigurable SoPC platform. In order to obtain optimized high performance pipelined architecture each process implementing repetitive conditional behavior with possible inter-iteration dependencies is scheduled under hardware resource constraints using "fabric cell synthesis tool" (FAST). The scheduling problem is defined and solved using constraints programming approach. This approach makes it possible to obtain optimal solutions in terms of execution time and number of registers for a number of real cases. Our method is illustrated using a simple example and a part of the "CORDIC" application (S.F. Hsiao et al., 1991). The final design is implemented on a reconfigurable platform that shows feasibility of our approach. Optimal schedules are achieved for both discussed applications.