Dipti, Shipra Gaur, Kavindra Kandpal, P. K. Misra, M. Goswami
{"title":"基于0.18 pJ/转换阶跃混合结构的ADC","authors":"Dipti, Shipra Gaur, Kavindra Kandpal, P. K. Misra, M. Goswami","doi":"10.1109/ASIANCON55314.2022.9908678","DOIUrl":null,"url":null,"abstract":"This paper presents the hybrid design of 8 bit ADC incorporating binary search ADC for area saving and flash ADC for higher speed operation. This ADC architecture is divided into two stages: the first stage is designed using binary search topology while the second stage is designed using flash architecture. The binary search stage is set to generate only 6 bits and flash stage is set to generate remaining 2 bits. With this hybrid configuration, the ADC consumes 12.8mW of power and sampling rate of 533 MSPS when operated at 1.8V.","PeriodicalId":429704,"journal":{"name":"2022 2nd Asian Conference on Innovation in Technology (ASIANCON)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 0.18 pJ/Conversion Step Hybrid Structure based ADC\",\"authors\":\"Dipti, Shipra Gaur, Kavindra Kandpal, P. K. Misra, M. Goswami\",\"doi\":\"10.1109/ASIANCON55314.2022.9908678\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the hybrid design of 8 bit ADC incorporating binary search ADC for area saving and flash ADC for higher speed operation. This ADC architecture is divided into two stages: the first stage is designed using binary search topology while the second stage is designed using flash architecture. The binary search stage is set to generate only 6 bits and flash stage is set to generate remaining 2 bits. With this hybrid configuration, the ADC consumes 12.8mW of power and sampling rate of 533 MSPS when operated at 1.8V.\",\"PeriodicalId\":429704,\"journal\":{\"name\":\"2022 2nd Asian Conference on Innovation in Technology (ASIANCON)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-08-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 2nd Asian Conference on Innovation in Technology (ASIANCON)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASIANCON55314.2022.9908678\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 2nd Asian Conference on Innovation in Technology (ASIANCON)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIANCON55314.2022.9908678","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 0.18 pJ/Conversion Step Hybrid Structure based ADC
This paper presents the hybrid design of 8 bit ADC incorporating binary search ADC for area saving and flash ADC for higher speed operation. This ADC architecture is divided into two stages: the first stage is designed using binary search topology while the second stage is designed using flash architecture. The binary search stage is set to generate only 6 bits and flash stage is set to generate remaining 2 bits. With this hybrid configuration, the ADC consumes 12.8mW of power and sampling rate of 533 MSPS when operated at 1.8V.
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