Asymmetric low-power FHSS algorithm

This paper documents development and basic testing of an asymmetric FHSS network. Asymmetric in a way that the network HUB or master consumes a lot of power, while the peripherals or slaves consume as little power as possible. To achieve good consumption, the input only sensors are sleeping most of the time and quickly synchronize into the FHSS scheme upon an event. The main idea explored in this paper is that network master frequently sends periodical beacons with information needed to synchronize into the network. The created network enables the connection of input only peripherals with input response time of 400 ms, while keeping the cumulative current consumption of 4.27 µA. The network was created for simple GFSK transceivers CC1200, produced by TI, which are controlled by Cortex-M processors, STM32F0 and STM32L0, produced by ST. The intended bandwidth is an SRD band h1.1 commonly known as 868MHz band. The principles explored in this paper can be used with different transceivers, different modulations or different MCUs. Some of the measurements are specific for the used hardware, but the results should be easy to extrapolate to any platform of interest.