以数据为中心的工作负载上的混合内存多维数据集性能表征

M. Gokhale, G. S. Lloyd, C. Macaraeg
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引用次数: 32

摘要

Hybrid Memory Cube是一款早期商用产品,体现了未来堆叠DRAM架构的特性,即大容量、高带宽、封装内存控制器和高速串行接口。我们通过在HMC FPGA板上结合仿真和执行,研究了Gen2 HMC在以数据为中心的工作负载上的性能和能量。一个内部FPGA仿真器已经被用来获取一小部分以数据为中心的基准测试的内存轨迹。我们的FPGA仿真器基于32位ARM处理器,非侵入性地捕获完整的内存访问跟踪,实时速度仅为20倍。我们已经开发了一些工具,可以在HMC板上运行来自多个基准测试的组合跟踪片段,从而提供了一种独特的功能来描述数据并行工作负载下的HMC性能和功耗使用情况。我们发现HMC的独立读和写通道并没有被以读为主导的数据中心工作负载很好地利用。我们的基准测试在HMC上达到峰值带宽的66% - 80%(对于具有50- 50读/写混合的32字节数据包,80gb /s),这表明在这些访问模式上,组合读/写通道可能显示出更高的利用率。随着对具有许多独立内存请求的高度并发应用程序工作负载的需求增加,带宽线性扩展到饱和。延迟相应增加,从极轻负载下的80 ns到高带宽下的130 ns不等。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Hybrid memory cube performance characterization on data-centric workloads
The Hybrid Memory Cube is an early commercial product embodying attributes of future stacked DRAM architectures, namely large capacity, high bandwidth, on-package memory controller, and high speed serial interface. We study the performance and energy of a Gen2 HMC on data-centric workloads through a combination of emulation and execution on an HMC FPGA board. An in-house FPGA emulator has been used to obtain memory traces for a small collection of data-centric benchmarks. Our FPGA emulator is based on a 32-bit ARM processor and non-intrusively captures complete memory access traces at only 20X slowdown from real time. We have developed tools to run combined trace fragments from multiple benchmarks on the HMC board, giving a unique capability to characterize HMC performance and power usage under a data parallel workload. We find that the HMC's separate read and write channels are not well exploited by read-dominated data-centric workloads. Our benchmarks achieve between 66% -- 80% of peak bandwidth (80 GB/s for 32-byte packets with 50--50 read/write mix) on the HMC, suggesting that combined read/write channels might show higher utilization on these access patterns. Bandwidth scales linearly up to saturation with increased demand on highly concurrent application workloads with many independent memory requests. There is a corresponding increase in latency, ranging from 80 ns on an extremely light load to 130 ns at high bandwidth.
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