finfet晶体管的研究:finfet晶体管在有源滤波器中的关键和文献综述

Arsen Ahmed Mohammede, Zaidoon Khalaf Mahmood, H. Demirel
{"title":"finfet晶体管的研究:finfet晶体管在有源滤波器中的关键和文献综述","authors":"Arsen Ahmed Mohammede, Zaidoon Khalaf Mahmood, H. Demirel","doi":"10.17993/3ctic.2023.121.65-81","DOIUrl":null,"url":null,"abstract":"For several decades, the development of metal-oxide-semiconductor field-effect transistors have made available to us better circuit time and efficiency per function with each successive generation of CMOS technology. However, basic product and manufacturing technology limitations will make continuing transistor scaling difficult in the sub-32 nm zone. Field impact transistors with fins were developed. offered as a viable solution to the scalability difficulties. Fin field effect transistors can be made in the same way as regular CMOS transistors, allowing for a quick transition to production. The use of inserted-oxide FinFET technology was presented as a solution to continue transistor scaling. Due to gate fringing electric fields through the added oxide (SiO2) layers, the electromagnetic integrity of an iFinFET is superior to that of a FinFET. We discovered that the proposed mobility model functions admirably and that the Joule effect mostly influences the drain current and the heat source. The major goal of this work is to compare the performance characteristics of combinational logic using CMOS and FinFET technology. The inverting gate is modelled in HSPICE simulation on a 32nm transistor size utilising CMOS and FinFET structures, and respective performances, such as energy consumed, are examined.","PeriodicalId":237333,"journal":{"name":"3C TIC: Cuadernos de desarrollo aplicados a las TIC","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Study of finfet transistor: critical and literature review in finfet transistor in the active filter\",\"authors\":\"Arsen Ahmed Mohammede, Zaidoon Khalaf Mahmood, H. Demirel\",\"doi\":\"10.17993/3ctic.2023.121.65-81\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"For several decades, the development of metal-oxide-semiconductor field-effect transistors have made available to us better circuit time and efficiency per function with each successive generation of CMOS technology. However, basic product and manufacturing technology limitations will make continuing transistor scaling difficult in the sub-32 nm zone. Field impact transistors with fins were developed. offered as a viable solution to the scalability difficulties. Fin field effect transistors can be made in the same way as regular CMOS transistors, allowing for a quick transition to production. The use of inserted-oxide FinFET technology was presented as a solution to continue transistor scaling. Due to gate fringing electric fields through the added oxide (SiO2) layers, the electromagnetic integrity of an iFinFET is superior to that of a FinFET. We discovered that the proposed mobility model functions admirably and that the Joule effect mostly influences the drain current and the heat source. The major goal of this work is to compare the performance characteristics of combinational logic using CMOS and FinFET technology. The inverting gate is modelled in HSPICE simulation on a 32nm transistor size utilising CMOS and FinFET structures, and respective performances, such as energy consumed, are examined.\",\"PeriodicalId\":237333,\"journal\":{\"name\":\"3C TIC: Cuadernos de desarrollo aplicados a las TIC\",\"volume\":\"21 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2023-03-31\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"3C TIC: Cuadernos de desarrollo aplicados a las TIC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.17993/3ctic.2023.121.65-81\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"3C TIC: Cuadernos de desarrollo aplicados a las TIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.17993/3ctic.2023.121.65-81","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

几十年来,随着每一代CMOS技术的发展,金属氧化物半导体场效应晶体管的发展为我们提供了更好的电路时间和每功能效率。然而,基本产品和制造技术的限制将使晶体管在32nm以下区域的持续缩放变得困难。研制了带翅片的场冲击晶体管。作为可伸缩性困难的可行解决方案提供。翅片场效应晶体管可以以与常规CMOS晶体管相同的方式制造,允许快速过渡到生产。使用插入氧化物FinFET技术是一个解决方案,以继续晶体管缩放。由于通过添加的氧化物(SiO2)层的栅极边缘电场,iFinFET的电磁完整性优于FinFET。我们发现所提出的迁移率模型具有良好的功能,焦耳效应主要影响漏极电流和热源。这项工作的主要目标是比较使用CMOS和FinFET技术的组合逻辑的性能特征。在HSPICE仿真中,利用CMOS和FinFET结构在32nm晶体管尺寸上建立了反相门,并检查了各自的性能,如能耗。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Study of finfet transistor: critical and literature review in finfet transistor in the active filter
For several decades, the development of metal-oxide-semiconductor field-effect transistors have made available to us better circuit time and efficiency per function with each successive generation of CMOS technology. However, basic product and manufacturing technology limitations will make continuing transistor scaling difficult in the sub-32 nm zone. Field impact transistors with fins were developed. offered as a viable solution to the scalability difficulties. Fin field effect transistors can be made in the same way as regular CMOS transistors, allowing for a quick transition to production. The use of inserted-oxide FinFET technology was presented as a solution to continue transistor scaling. Due to gate fringing electric fields through the added oxide (SiO2) layers, the electromagnetic integrity of an iFinFET is superior to that of a FinFET. We discovered that the proposed mobility model functions admirably and that the Joule effect mostly influences the drain current and the heat source. The major goal of this work is to compare the performance characteristics of combinational logic using CMOS and FinFET technology. The inverting gate is modelled in HSPICE simulation on a 32nm transistor size utilising CMOS and FinFET structures, and respective performances, such as energy consumed, are examined.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信