{"title":"考虑HPC/AI/网络应用中逻辑与HBM芯片之间y轴偏移的信号完整性(SI)感知HBM2e/3中间层设计方法","authors":"Taeyun Kim, Chanmin Jo, S. Moon","doi":"10.1109/ECTC32696.2021.00206","DOIUrl":null,"url":null,"abstract":"This work demonstrates an efficient signal integrity (SI) aware routing design method considering system-level SI characteristics floor-planning for 2.5D interposer for the AI/HPC/Network solutions in early stage. The proposed method, system-level SI aware interposer design methodology (SSIDM) can accurately estimate the SI characteristics based on limited design information in early stage and even derive a design guideline for efficient SI aware post-layout design process. Using the novel design guidelines provided in this work can help the designer to smoothly transition designs from HBM2e to HBM3 with sufficient SI margins.","PeriodicalId":351817,"journal":{"name":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Signal Integrity(SI) aware HBM2e/3 interposer design approach considering y-axis offset between logic and HBM die for HPC/AI/Network applications\",\"authors\":\"Taeyun Kim, Chanmin Jo, S. Moon\",\"doi\":\"10.1109/ECTC32696.2021.00206\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work demonstrates an efficient signal integrity (SI) aware routing design method considering system-level SI characteristics floor-planning for 2.5D interposer for the AI/HPC/Network solutions in early stage. The proposed method, system-level SI aware interposer design methodology (SSIDM) can accurately estimate the SI characteristics based on limited design information in early stage and even derive a design guideline for efficient SI aware post-layout design process. Using the novel design guidelines provided in this work can help the designer to smoothly transition designs from HBM2e to HBM3 with sufficient SI margins.\",\"PeriodicalId\":351817,\"journal\":{\"name\":\"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)\",\"volume\":\"73 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ECTC32696.2021.00206\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE 71st Electronic Components and Technology Conference (ECTC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECTC32696.2021.00206","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Signal Integrity(SI) aware HBM2e/3 interposer design approach considering y-axis offset between logic and HBM die for HPC/AI/Network applications
This work demonstrates an efficient signal integrity (SI) aware routing design method considering system-level SI characteristics floor-planning for 2.5D interposer for the AI/HPC/Network solutions in early stage. The proposed method, system-level SI aware interposer design methodology (SSIDM) can accurately estimate the SI characteristics based on limited design information in early stage and even derive a design guideline for efficient SI aware post-layout design process. Using the novel design guidelines provided in this work can help the designer to smoothly transition designs from HBM2e to HBM3 with sufficient SI margins.
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