{"title":"用于通信系统的6位线性二进制射频DAC，采用0.25µm SiGe BiCMOS","authors":"M. Khafaji, H. Gustat, C. Scheytt","doi":"10.1109/MWSYM.2010.5517724","DOIUrl":null,"url":null,"abstract":"This paper presents a circuit technique to improve the frequency domain behavior of the binary weighted digital to analog convertors (DAC). It is shown that by adding a current buffer stage, the effect of one of the major drawbacks in this architecture, the impedance variation in every stage, is reduced. To verify the method, a fully binary 6bit 20.5Gsps DAC with 1W power dissipation and measured SFDR higher than 28.2dBc up to 6.2GHz input bandwidth was fabricated. The DAC produces 1Vpp differential output, and less than 60ps full scale rise time.","PeriodicalId":341557,"journal":{"name":"2010 IEEE MTT-S International Microwave Symposium","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2010-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"A 6 bit linear binary RF DAC in 0.25µm SiGe BiCMOS for communication systems\",\"authors\":\"M. Khafaji, H. Gustat, C. Scheytt\",\"doi\":\"10.1109/MWSYM.2010.5517724\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a circuit technique to improve the frequency domain behavior of the binary weighted digital to analog convertors (DAC). It is shown that by adding a current buffer stage, the effect of one of the major drawbacks in this architecture, the impedance variation in every stage, is reduced. To verify the method, a fully binary 6bit 20.5Gsps DAC with 1W power dissipation and measured SFDR higher than 28.2dBc up to 6.2GHz input bandwidth was fabricated. The DAC produces 1Vpp differential output, and less than 60ps full scale rise time.\",\"PeriodicalId\":341557,\"journal\":{\"name\":\"2010 IEEE MTT-S International Microwave Symposium\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-05-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 IEEE MTT-S International Microwave Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MWSYM.2010.5517724\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE MTT-S International Microwave Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSYM.2010.5517724","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 6 bit linear binary RF DAC in 0.25µm SiGe BiCMOS for communication systems
This paper presents a circuit technique to improve the frequency domain behavior of the binary weighted digital to analog convertors (DAC). It is shown that by adding a current buffer stage, the effect of one of the major drawbacks in this architecture, the impedance variation in every stage, is reduced. To verify the method, a fully binary 6bit 20.5Gsps DAC with 1W power dissipation and measured SFDR higher than 28.2dBc up to 6.2GHz input bandwidth was fabricated. The DAC produces 1Vpp differential output, and less than 60ps full scale rise time.
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