Stress Enhanced Performance Analysis for Trigate FinFETs at 7nm Node

Short channel effect becomes a serious concern below 22nm technology node. This can be overcome by multigate devices such as double gate (DG), trigate (TG). Trigate FinFET structures have shown great potential for both digital and analog applications. In this work, we have simulated a realistic PMOS bulk-Si FinFET with epi-SiGe as a source/drain (S/D) stressor at a 7nm technology node. The strain enhancement mechanisms have been used in the diamond-shaped bridges patterned on SiGe S/D stressor. The stress in the channel due to epitaxial S/D stressor has been calculated using the stress history model and the theory of elasticity. A 30% improvement of the ‘on current’ in the channel as compared to the device without stress is demonstrated.