{"title":"使用固定功率预算的频率缩放多核加速模型","authors":"Seungwon Lee, Seung Hun Kim, W. Ro","doi":"10.1109/ELINFOCOM.2014.6914403","DOIUrl":null,"url":null,"abstract":"Utilization of a core with delay faults by frequency scaling reduces performance degradation in a multicore processor. When the frequency of a delay fault core is decreased, frequencies of the rest cores can be increased within a fixed power budget since the amount of dynamic power is proportional to the clock frequency. We propose two speedup models based on modified Amdahl's law for the frequency scaling of a multicore architecture. From the models, we derive an attainable maximum speedup of a multicore processor with a delay fault core.","PeriodicalId":360207,"journal":{"name":"2014 International Conference on Electronics, Information and Communications (ICEIC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Multicore speedup models using frequency scaling with fixed power budget\",\"authors\":\"Seungwon Lee, Seung Hun Kim, W. Ro\",\"doi\":\"10.1109/ELINFOCOM.2014.6914403\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Utilization of a core with delay faults by frequency scaling reduces performance degradation in a multicore processor. When the frequency of a delay fault core is decreased, frequencies of the rest cores can be increased within a fixed power budget since the amount of dynamic power is proportional to the clock frequency. We propose two speedup models based on modified Amdahl's law for the frequency scaling of a multicore architecture. From the models, we derive an attainable maximum speedup of a multicore processor with a delay fault core.\",\"PeriodicalId\":360207,\"journal\":{\"name\":\"2014 International Conference on Electronics, Information and Communications (ICEIC)\",\"volume\":\"48 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-10-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 International Conference on Electronics, Information and Communications (ICEIC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ELINFOCOM.2014.6914403\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 International Conference on Electronics, Information and Communications (ICEIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ELINFOCOM.2014.6914403","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Multicore speedup models using frequency scaling with fixed power budget
Utilization of a core with delay faults by frequency scaling reduces performance degradation in a multicore processor. When the frequency of a delay fault core is decreased, frequencies of the rest cores can be increased within a fixed power budget since the amount of dynamic power is proportional to the clock frequency. We propose two speedup models based on modified Amdahl's law for the frequency scaling of a multicore architecture. From the models, we derive an attainable maximum speedup of a multicore processor with a delay fault core.