Design and Implementation of an Improved BIST Architecture for ROM

Input vector monitoring online testing schemes perform testing during the normal operation of the circuit. These schemes are evaluated based on hardware overhead and concurrent test latency (CTL), also well suited for modules requiring exhaustive testing, such as Read Only Memories (ROMs). In this work we present an input vector monitoring concurrent BIST scheme specially designed for the testing of ROM modules along with an error detecting unit which can detect error of corresponding bit position. By using circuitry already existing for the memory module, the hardware overhead, power and the delay, compared to previously proposed schemes, is significantly reduced.