V. Vlagkoulis, Aitzan Sari, Juljan Proko, Dimitrios Zografakis, M. Psarakis, Antonios Tavoularis, G. Furano, C. Boatella-Polo, C. Poivey, V. Ferlet-Cavrois, M. Kastriotou, Pablo Fernández Martínez, R. G. Alía
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Configuration Memory Scrubbing of the Xilinx Zynq-7000 FPGA using a Mixed 2-D Coding Technique
The paper presents a configuration memory scrubbing approach for the Xilinx Zynq-7000 devices. The approach combines the embedded Error Correction Code of the configuration memory frames and an interframe, interleaved parity scheme to form a mixed two-dimensional (2-D) error correction code. The 2-D coding scheme detects and corrects single and multiple bit upsets in the configuration memory of the Xilinx Zynq-7000 FPGA device. The proposed scrubbing methodology has been evaluated under heavy ion irradiation and achieved 100% error correction coverage.
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