Modeling regular, process—structured networks*

An interesting strategy to exploit micro-technology is to interconnect microcomputers (i.e., microprocessor with local memory) in a regular dataflow network of low degree. The network is regular so that each computer is a similar "building block" with regard to the number of connecting data buses. The number of buses is small not only because microcomputers are inherently limited in their bus capacity but also because many incident buses lead to switching and "memory port" complexity, which is difficult to handle by micro-circuits. Such complexity is one of the reasons why shared memory "mainframe" computers are relatively expensive. In essence, the low-degree, regular network approach replaces the hard-wired switching with programmed message-passing. Since the processor node will not be fully utilized by productive computing, some of the capacity can profitably be used for such message-handling.