{"title":"一种用于5G通信的紧凑型39 ghz 17.2 dbm功率放大器","authors":"Yun Wang, Rui Wu, K. Okada","doi":"10.1109/RFIT.2018.8524130","DOIUrl":null,"url":null,"abstract":"This paper presents design of a 39-GHz power amplifier for fifth-generation (5G) mobile communication in millimeter-wave. The power amplifier consists of two differential capacitive-neutralized common-source stages. Low-loss transformers are employed for matching network in each stage. With 1.1-V supply, the power amplifier achieves a small-signal gain of 17 dB, saturated output power (PSAT) of 17.2 dBm, and 1-dB compression point (P1dB) of 15.5 dBm at 39 GHz. The amplifier has a maximum power-added efficiency (PAEMAX) of 31.2% and 30.2% at P1dB. The amplifier has an average output power of 9.0 dBm and 10.0% PAE with −25 dBc EVM. The amplifier has been fabricated in standard 65-nm CMOS and occupies an area of 0.081 mm2.","PeriodicalId":297122,"journal":{"name":"2018 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"A Compact 39-GHz 17.2-dBm Power Amplifier for 5G Communication in 65-nm CMOS\",\"authors\":\"Yun Wang, Rui Wu, K. Okada\",\"doi\":\"10.1109/RFIT.2018.8524130\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents design of a 39-GHz power amplifier for fifth-generation (5G) mobile communication in millimeter-wave. The power amplifier consists of two differential capacitive-neutralized common-source stages. Low-loss transformers are employed for matching network in each stage. With 1.1-V supply, the power amplifier achieves a small-signal gain of 17 dB, saturated output power (PSAT) of 17.2 dBm, and 1-dB compression point (P1dB) of 15.5 dBm at 39 GHz. The amplifier has a maximum power-added efficiency (PAEMAX) of 31.2% and 30.2% at P1dB. The amplifier has an average output power of 9.0 dBm and 10.0% PAE with −25 dBc EVM. The amplifier has been fabricated in standard 65-nm CMOS and occupies an area of 0.081 mm2.\",\"PeriodicalId\":297122,\"journal\":{\"name\":\"2018 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)\",\"volume\":\"37 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RFIT.2018.8524130\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIT.2018.8524130","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Compact 39-GHz 17.2-dBm Power Amplifier for 5G Communication in 65-nm CMOS
This paper presents design of a 39-GHz power amplifier for fifth-generation (5G) mobile communication in millimeter-wave. The power amplifier consists of two differential capacitive-neutralized common-source stages. Low-loss transformers are employed for matching network in each stage. With 1.1-V supply, the power amplifier achieves a small-signal gain of 17 dB, saturated output power (PSAT) of 17.2 dBm, and 1-dB compression point (P1dB) of 15.5 dBm at 39 GHz. The amplifier has a maximum power-added efficiency (PAEMAX) of 31.2% and 30.2% at P1dB. The amplifier has an average output power of 9.0 dBm and 10.0% PAE with −25 dBc EVM. The amplifier has been fabricated in standard 65-nm CMOS and occupies an area of 0.081 mm2.