用于40gbit /s光通信链路的时钟恢复集成电路

R. Yu, R. Pierson, P. Zampardi, K. Runge, A. Campana, D. Meeker, K. Wang, A. Petersen, J. Bowers
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引用次数: 10

摘要

采用先进的AlGaAs-GaAs HBT工艺实现了三种封装时钟恢复集成电路:微分/整流电路、延迟/倍增电路和鉴相电路。封装ic的性能足以满足高达40gbit /s的光通信链路的时钟恢复。在30 Gbit/s伪随机序列输入下,结合这些ic的锁相环很容易获得并保持锁相,证明了这些组件的优异系统性能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Packaged clock recovery integrated circuits for 40 Gbit/s optical communication links
Three packaged clock recovery integrated circuits: a differentiate/rectify circuit, a delay/multiply circuit, and a phase detector circuit, were implemented in an advanced AlGaAs-GaAs HBT process. The packaged ICs show performance adequate for clock recovery for optical communication links of up to at least 40 Gbit/s. With a 30 Gbit/s pseudo-random sequence input, a phase-locked loop incorporating these ICs readily acquired and maintained phase lock, demonstrating the excellent system performance of these components.
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