R. Yu, R. Pierson, P. Zampardi, K. Runge, A. Campana, D. Meeker, K. Wang, A. Petersen, J. Bowers
{"title":"用于40gbit /s光通信链路的时钟恢复集成电路","authors":"R. Yu, R. Pierson, P. Zampardi, K. Runge, A. Campana, D. Meeker, K. Wang, A. Petersen, J. Bowers","doi":"10.1109/GAAS.1996.567824","DOIUrl":null,"url":null,"abstract":"Three packaged clock recovery integrated circuits: a differentiate/rectify circuit, a delay/multiply circuit, and a phase detector circuit, were implemented in an advanced AlGaAs-GaAs HBT process. The packaged ICs show performance adequate for clock recovery for optical communication links of up to at least 40 Gbit/s. With a 30 Gbit/s pseudo-random sequence input, a phase-locked loop incorporating these ICs readily acquired and maintained phase lock, demonstrating the excellent system performance of these components.","PeriodicalId":365997,"journal":{"name":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium. 18th Annual Technical Digest 1996","volume":"230 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"Packaged clock recovery integrated circuits for 40 Gbit/s optical communication links\",\"authors\":\"R. Yu, R. Pierson, P. Zampardi, K. Runge, A. Campana, D. Meeker, K. Wang, A. Petersen, J. Bowers\",\"doi\":\"10.1109/GAAS.1996.567824\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Three packaged clock recovery integrated circuits: a differentiate/rectify circuit, a delay/multiply circuit, and a phase detector circuit, were implemented in an advanced AlGaAs-GaAs HBT process. The packaged ICs show performance adequate for clock recovery for optical communication links of up to at least 40 Gbit/s. With a 30 Gbit/s pseudo-random sequence input, a phase-locked loop incorporating these ICs readily acquired and maintained phase lock, demonstrating the excellent system performance of these components.\",\"PeriodicalId\":365997,\"journal\":{\"name\":\"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium. 18th Annual Technical Digest 1996\",\"volume\":\"230 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-11-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium. 18th Annual Technical Digest 1996\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/GAAS.1996.567824\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium. 18th Annual Technical Digest 1996","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GAAS.1996.567824","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Packaged clock recovery integrated circuits for 40 Gbit/s optical communication links
Three packaged clock recovery integrated circuits: a differentiate/rectify circuit, a delay/multiply circuit, and a phase detector circuit, were implemented in an advanced AlGaAs-GaAs HBT process. The packaged ICs show performance adequate for clock recovery for optical communication links of up to at least 40 Gbit/s. With a 30 Gbit/s pseudo-random sequence input, a phase-locked loop incorporating these ICs readily acquired and maintained phase lock, demonstrating the excellent system performance of these components.