一种新的通用可重构数字信号处理器体系结构

15th International Conference on Advanced Computing and Communications (ADCOM 2007) Pub Date : 2007-12-18 DOI:10.1109/ADCOM.2007.21

J. Basu, Md. Sahidullah, A. Sinha

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引用次数: 76

摘要

本文提出了一种新的可重构数字信号处理(DSP)体系结构和算法，其基本构建模块是高性能加法器、减法器、乘法器等。该架构的设计考虑了高性能、低动态配置延迟、灵活性和低功耗。详细讨论了基本构件之间的互连问题，并提出了一种新的方案。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A New Generalized Reconfigurable Architecture for Digital Signal Processor

In this paper a novel re-configurable digital signal processing (DSP) architecture and algorithm has been proposed where basic building blocks are high performance adders, subtracters, multipliers etc. The architecture has been conceived keeping high performance, low dynamic configuration latency, flexibility and low power consumption in view. Issues involving interconnection among the basic building blocks have been dealt with in details and a new scheme is proposed.

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15th International Conference on Advanced Computing and Communications (ADCOM 2007)

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