采用0.5um CMOS技术的锁相环DLS565的全定制设计和表征

2014 International Conference on Humanoid, Nanotechnology, Information Technology, Communication and Control, Environment and Management (HNICEM) Pub Date : 2014-11-01 DOI:10.1109/HNICEM.2014.7016240

Kenneth Martin C. Atendido, Justin Daniel C. Co, Jose Gianmarco B. Navarro, Pamela Candice H. Garcia, Alexander C. Abad

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引用次数: 0

摘要

DLS565是一款锁相环(PLL)集成电路(IC)设计项目，采用0.5um CMOS技术在所有工艺角库(TT, FF, SS, FS, SF)上进行仿真。无键合盘的锁相环的最终IC设计布局约为0.46mm × 0.5mm。测量了DLS565的参数，并与市售的LM565C和NE565进行了比较。它在±2.5 V的电源电压下工作，最大功耗约为22 mW。DLS565能够捕获低至15Hz和高至1.12MHz的频率。

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Full-custom design and characterization of a phase locked loop — DLS565 using 0.5um CMOS technology

The DLS565 is a Phase-locked loop (PLL) Integrated Circuit (IC) design project simulated on all process corner libraries (TT, FF, SS, FS, SF) using 0.5um CMOS technology. The final IC design layout of the PLL without bonding pads covers approximately 0.46mm × 0.5mm. The parameters of the DLS565 were measured and compared to the commercially available LM565C and NE565. It operates with a supply voltage of ±2.5 V with a maximum power dissipation of approximately 22 mW. DLS565 was able to capture frequencies as low as 15Hz and as high as 1.12MHz.

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2014 International Conference on Humanoid, Nanotechnology, Information Technology, Communication and Control, Environment and Management (HNICEM)

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