Frequency Optimized FPGA-Based Digital FIR Filters with Data Inputs and Coefficients of Large Size

Field Programmable Gate Arrays (FPGAs) are used in realizing real-life applications. Finite Impulse Response (FIR) is widely used in digital signal processing applications. Digital FIRs are made from multiplication and addition operations and registers. In this paper, we target digital FIRs with data inputs and coefficients of large size. Since embedded multiplier blocks in FPGAs are of limited input sizes, this implies that the inputs of the filters have to be segmented first. Next, the small multiplications have to be carried out using the embedded blocks and the resulting partial products have to be added together to get the final result. In this paper, using the state of the art results, we synthesis FIRs on FPGAs with data inputs and coefficients of sizes ranging from 20 to 50 bits. Experimental results show that both the frequency and the area can be optimized for the case of Xilinx Spartan 3 FPGAs. For Xilinx Vertix 6 FPGAs, the frequency has been improved while the area has been increased for some sizes and has been decreased in other cases; when the number of used DSP blocks is reduced, some area metrics have been increased, and viceversa.