Low-power adaptive edge decision feedback equalizer for serial links with 4PAM signaling

This paper presents a low-power adaptive edge decision feedback equalizer (DFE) for 10 giga-bits-per-second (Gbps) serial links with 4 PAM (pulse-amplitude-modulation) signaling. Optimal tap coefficients are obtained adaptively using a sign-sign least-mean-square (SS-LMS) algorithm that minimizes the jitter of equalized data. Low-voltage-differential-signaling (LVDS) tap generators that double DFE strength without increasing power consumption are used. Power reduction is also achieved by only activating the tap generator corresponding to the incoming data and sharing slicers for determining data state, the sign of data jitter, and bang-bang phase detection. A frequency locked-loop locked to an external frequency reference and a bang-bang phase-locked loop locked to the edge of equalized data, both sharing the same active inductor ring oscillator with separate frequency and phase tunings, are employed for clock recovery. The effectiveness of the proposed edge DFE is validated using a 10 Gbps 4PAM serial link designed in a 65 nm CMOS technology over a wire channel with 12 dB loss at baud-rate frequency. Simulation results demonstrated that the proposed adaptive edge DFE is capable of achieving 46% vertical opening and 60\% horizontal eye-opening while consuming 26.24 mW.