A. G. Amat, G. Montorsi, S. Benedetto, D. Vogrig, A. Neviani, A. Gerosa
{"title":"模拟涡轮解码器的UMTS标准","authors":"A. G. Amat, G. Montorsi, S. Benedetto, D. Vogrig, A. Neviani, A. Gerosa","doi":"10.1109/ISIT.2004.1365329","DOIUrl":null,"url":null,"abstract":"The design and test results of a three-metal, double-poly, 0.35 μm; CMOS analog turbo decoder for the rate-1/3, block length 40, UMTS turbo code, are presented. A discrete-time model of analog decoding networks is also presented. This model can be used as a tool to both predict chip performance in a short time and give design guidelines for complex decoders, for which circuit-level simulations are impractical.","PeriodicalId":269907,"journal":{"name":"International Symposium onInformation Theory, 2004. ISIT 2004. Proceedings.","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2004-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":"{\"title\":\"An analog turbo decoder for the UMTS standard\",\"authors\":\"A. G. Amat, G. Montorsi, S. Benedetto, D. Vogrig, A. Neviani, A. Gerosa\",\"doi\":\"10.1109/ISIT.2004.1365329\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The design and test results of a three-metal, double-poly, 0.35 μm; CMOS analog turbo decoder for the rate-1/3, block length 40, UMTS turbo code, are presented. A discrete-time model of analog decoding networks is also presented. This model can be used as a tool to both predict chip performance in a short time and give design guidelines for complex decoders, for which circuit-level simulations are impractical.\",\"PeriodicalId\":269907,\"journal\":{\"name\":\"International Symposium onInformation Theory, 2004. ISIT 2004. Proceedings.\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-07-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"15\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Symposium onInformation Theory, 2004. ISIT 2004. Proceedings.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISIT.2004.1365329\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Symposium onInformation Theory, 2004. ISIT 2004. Proceedings.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISIT.2004.1365329","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The design and test results of a three-metal, double-poly, 0.35 μm; CMOS analog turbo decoder for the rate-1/3, block length 40, UMTS turbo code, are presented. A discrete-time model of analog decoding networks is also presented. This model can be used as a tool to both predict chip performance in a short time and give design guidelines for complex decoders, for which circuit-level simulations are impractical.