RF CMOS all inversion region design based on gm/ID: the non-linear case of an envelope detector

All inversion region CMOS design and the gm/ID method have been previously applied to achieve optimized RF CMOS designs for circuits, such as an LNA, with performance determined by the linearized, small signal, parameters of the transistor. In this work we show that this approach is very useful also in the case of an envelope detector, whose operation is based on the second order non-linear behavior of the transistor (determined by the second derivative of the current vs. voltage characteristic). A semi-empirical, look-up table based, model of the MOS transistor is applied. Through it, it is determined the inversion level (directly related to the gms/ID ratio) where the conversion gain is maximized. A novel figure of merit that only depends on the inversion level is proposed to aid the design. The predictions are verified against measurements results, both at the transistor and circuit level. The considered circuit is a MOS Envelope Detector with on-chip matching network for 2.4GHz in 0.13 m CMOS technology.