在硬件/软件协同设计中探索硬件/软件并行性的RISC架构

Proceedings IEEE Symposium and Workshop on Engineering of Computer-Based Systems Pub Date : 1996-03-11 DOI:10.1109/ECBS.1996.494564

L. Carro, A. Susin

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引用次数: 1

摘要

本文描述了对嵌入式类risc处理器架构的一些修改，以更好地探索硬件/软件协同设计环境下的硬件/软件并行性。结果表明，包含一个指令存储器允许并行执行应用软件和最终专用硬件。两种不同的RISC微处理器显示了积极的结果。本文还报告了实验结果，特别是提出的修改应用于感应电机控制算法。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A RISC architecture to explore HW/SW parallelism in HW/SW codesign

The paper describes some modifications on the architecture of embedded RISC-like processors to better explore HW/SW (hardware/software) parallelism in a HW/SW co-design environment. It is shown that the inclusion of an instruction memory allows parallel execution of the application SW and eventual dedicated HW. Positive results are shown for two different RISC microprocessors. The paper also reports experimental results, particularly the proposed modifications applied to an induction motor control algorithm.

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Proceedings IEEE Symposium and Workshop on Engineering of Computer-Based Systems

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