超大规模集成电路系统的面积-时间高效算法元件

1987 IEEE 8th Symposium on Computer Arithmetic (ARITH) Pub Date : 1987-05-18 DOI:10.1109/ARITH.1987.6158717

Ramautar Sharma

{"title":"超大规模集成电路系统的面积-时间高效算法元件","authors":"Ramautar Sharma","doi":"10.1109/ARITH.1987.6158717","DOIUrl":null,"url":null,"abstract":"Algorithms for the high speed binary arithmetic operations of addition and multiplication in a VLSI environment are analyzed for area-time efficiency. It is shown that some schemes for addition and multiplication, although good for stand-alone designs, fail to provide both area and time efficiencies simultaneously. Solutions that yield area-time efficient practical implementations of these arithmetic functions are described.","PeriodicalId":424620,"journal":{"name":"1987 IEEE 8th Symposium on Computer Arithmetic (ARITH)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1987-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Area-time efficient arithmetic elements for VLSI systems\",\"authors\":\"Ramautar Sharma\",\"doi\":\"10.1109/ARITH.1987.6158717\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Algorithms for the high speed binary arithmetic operations of addition and multiplication in a VLSI environment are analyzed for area-time efficiency. It is shown that some schemes for addition and multiplication, although good for stand-alone designs, fail to provide both area and time efficiencies simultaneously. Solutions that yield area-time efficient practical implementations of these arithmetic functions are described.\",\"PeriodicalId\":424620,\"journal\":{\"name\":\"1987 IEEE 8th Symposium on Computer Arithmetic (ARITH)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1987-05-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1987 IEEE 8th Symposium on Computer Arithmetic (ARITH)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ARITH.1987.6158717\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1987 IEEE 8th Symposium on Computer Arithmetic (ARITH)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ARITH.1987.6158717","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 5

摘要

分析了VLSI环境下高速二进制加法和乘法运算算法的面积-时间效率。结果表明，一些加法和乘法的方案，虽然对独立设计很好，但不能同时提供面积和时间效率。描述了产生这些算术函数的面积-时间有效的实际实现的解决方案。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Area-time efficient arithmetic elements for VLSI systems

Algorithms for the high speed binary arithmetic operations of addition and multiplication in a VLSI environment are analyzed for area-time efficiency. It is shown that some schemes for addition and multiplication, although good for stand-alone designs, fail to provide both area and time efficiencies simultaneously. Solutions that yield area-time efficient practical implementations of these arithmetic functions are described.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

1987 IEEE 8th Symposium on Computer Arithmetic (ARITH)

自引率

0.00%

发文量