Memory module selection for high level synthesis

High level synthesis studies have produced many tools which enable us to design the processing unit of applications. The emergence of new communication services has lead to significant growth in the amount of data to be processed in VLSI chips. It involves to synthesis of memory architecture which enables us to satisfy all the application constraints. To obtain this organization, the first step is to select memory from a component library. This paper suggests a formulation of this problem through a minimization of function under constraints. Our approach takes place after the processing unit synthesis and our methodology can be applied to FPGA chips.